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Describe the concept of the fetch-execute cycle
Describe factors affecting computer performance
In this lesson, we will cover:
The fetch-execute cycle
Factors affecting computer system performance
From this diagram we should also know that the CPU is broken down into 3 main parts:
Control Unit
The control unit controls the order of execution and the timing of all instructions
Arithmetic and Logic Unit (ALU)
The ALU performs the calculations for the processor and evaluates logical decisions.
Registers
The registers are temporary storage spaces for data. They are found directly on the CPU and are often only a few bytes in size.
| Control Line | Function |
|---|---|
| Clock | Generates a constant pulse (measured in MHz). One operation will be carried out per pulse |
| Read | Signals that the processor wishes to read data from the memory |
| Write | Signals that the processor wishes to write data to the memory |
| Reset | Causes the processor to halt execution of current instruction. All registers cleared and machine reboots |
| Interrupt (IRQ) | Notifies the processor that an external event has occurred such as I/O from a device. This type of interrupt can be ignored. |
| Non-Maskable Interrupt (NMI) | This is an interrupt that CANNOT be ignored such as a low power failure notification |
Clock speed is the number of pulses that occur in a second. Which is measured in hertz
1 clock pulse = 1 hertz
1000 clock pulses = 1000 hertz = 1 kilohertz
1000 kilohertz = 1 megahertz
1000 megahertz = 1 gigahertz
1000 gigahertz = 1 terahertz
The primary role of the ALU is arithmetic calculations, including addition, subtraction, multiplication and division.
In relation to logic it will perform calculations such as AND/OR/NOT (such as those used in programming or in a processor instruction)
One particular register used by the ALU is the accumulator which holds the results of calculations. (Intel calls this the EAX)
Registers are very small memory locations found on the CPU itself. Because they are found on the CPU die, they are incredibly quick to access.
Registers are used to store small amounts of data whilst a program is being executed. The data they tend to hold varies from program data, to instructions to memory locations.
Registers are very close to the processing units of the CPU (such as the ALU and control unit) to improve system performance, but they are also very small and limited to around 64 bits (8 bytes).
Below is a simple C program to add two numbers in x86 Assembly Code:
add(int, int):
push rbp
mov rbp, rsp
mov DWORD PTR [rbp-4], edi
mov DWORD PTR [rbp-8], esi
mov eax, DWORD PTR [rbp-4]
add eax, DWORD PTR [rbp-8]
pop rbp
retSome specialist registers are shown below:
| Register name | Description |
|---|---|
| Instruction Register | Holds the address in memory of the next instruction to be executed |
| Memory Address Register (MAR) | This is used to hold a value representing the address in memory that the processor needs to access. This would be connected to the address bus |
| Memory Data Register (MDR) | This is used to gold data read from or being written to memory. Connected to the data bus |
| Program Counter | Stores the instruction number that the program is currently executing. On x86 machines this is called the instruction pointer. |
Buses are lines (wires) that connect different parts of a computer together.
If you flip a motherboard over, you can see all the lines (called traces) that show all the buses.
Data Bus – Used to carry data to and from the CPU and memory. It holds a binary word. The data bus is bidirectional.
Address Bus - Used to carry the address of the memory location that is being used. It is unidirectional.
Control Bus – This doesn’t carry data but has a number of status signals it can send (reset, interrupt etc.)
unidirectional = one way
bidirectional = two way
A binary word is the number of bits that can be transferred by the data bus in a single operation.
Most PCs just now have a word length of 32 or 64 bits. Meaning the data bus can carry 16 (WORD), 32 (DWORD) or 64 (QWORD) bits in a single operation.
Changing the width of the data bus means that we can move more or less data in a single operation - this would lead to increased performance due to less operations required to move
Changing the width of the address bus means that we can address more memory - this wouldn’t necessarily lead to an increase in performance in all cases
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16 bit address bus
Changing the width of the data bus means that we can move more or less data in a single operation - this would lead to increased performance due to less operations required to move
Changing the width of the address bus means that we can address more memory - this wouldn’t necessarily lead to an increase in performance in all cases
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32 bit address bus
Explain why increasing the width of the data bus will improve the system performance.
2 marks
SQP Q11 b)
The wider the data bus, the more bits that can be transferred (1 mark) in a single operation (1 mark)
The memory address of the next instruction is placed on the Memory Address Register
The processor activates the read line on the control bus
The instruction is fetched from the memory location using the data bus and stored in the Instruction Register
The instruction in the Instruction Register is then interpreted by the decoder and executed
Stage
1
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From what we just looked at, write down the four stages of the fetch-execute cycle and describe them.
A multi-core processor is a processor with two or more separate processing units (cores).
Each core contains an ALU, Control Unit and Registers.
The greater the number of cores on a processor, the greater the number of instructions that can be carried out simultaneously.
However, it’s not always possible to share tasks between cores.
An AMD EPYC chip is shown to the right. It consists of multiple smaller chiplets which themselves have multiple cores. EPYC processors can have up to 128 cores as of 2023.
It's also possible to get motherboards that can take multiple processors themselves.
The board pictured here is a dual AMD EPYC board that can take two 128 core EPYC CPUs and up to 1.2TB of main memory.
Parallelism is a big research area in computer science today.
We already know that the data bus is used to carry data to and from the processor.
Each cycle of the fetch-execute cycle requires data to be moved along the data bus.
Increasing the width of the data bus, increases the amount of data that can be transported in a single cycle.
Cache memory is a small amount of fast accessible memory usually on the same chip as the processor.
The processor will check cache for data before accessing the main memory.
If it finds data or an instruction, this is known as a cache ‘hit’, resulting in improved performance. If the instruction is not present, then a cache ‘miss’ occurs and a slower main memory is accessed.
Many computers use multiple levels of cache, with small caches backed up by larger, slower caches.
There are different levels of cache memory:
| Level | Description |
|---|---|
| L1 | In the processor core, generally around about 64KB |
| L2 | Generally attached to the core, around about 256KB per core |
| L3 | Generally shared between all cores, between 4MB and 32MB |
The processor always checks the fastest cache first. If the hit is not found it goes to the next fastest level and so on.
Cache memory is used to store frequently used data and instructions.
Clock speed is the measure of how many instruction cycles the system can work through within one second.
Clock pulses are used to trigger components to take their next step.
The higher the clock speed, the faster the computer can complete a set of instructions.
It is possible with some CPUs (for example Intel K series CPUs and all AMD Ryzen CPUs) to push them passed their set clock speed.
This is called overclocking.
The stability of a system can suffer as the clock speed gets higher, and since power consumption is directly proportional to the frequency the power draw can increase. Often overclockers tend to overvolt the system as well as overclock it to improve stability.
Increasing clock speed is one method of improving processor performance.
a) State one other method of improving processor performance.
1 mark
b) Explain how your answer to part (a) improves performance
1 mark
2021 Q2 (a) & (b)
System Performance questions come up almost every year in the exam.
Make sure you know what can improve it and how it improves it
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